Arm Holdings’ [NASDAQ:ARM] core business is to license so-called reduced instruction set computer (RISC) architecture based CPU designs to chip designers, such as Apple NASDAQ:AAPL or QualcommNASDAQ:QCOM.
However, several companies have recently started developing CPUs based on a 100% royalty free open-source RISC architecture called RISC-V which can be used to achieve many of the same things Arm’s core products provide, of course cutting out any need to pay licensing fees to Arm. This could be a long-term threat to their business.
Advanced RISC Machines (Arm)
Those aware of Arm’s history may know that it was officially founded under the name Advanced RISC Machines in 1990, being spun out from the Cambridge-based Acorn Computers as a company to license their central processing unit (CPU) intellectual property (IP). This followed the development of the first “ARM” CPU by Acorn Computers in the 1980s, called the Acorn RISC Machine.
Since then, Arm Holdings have grown to a market capitalization of $175 billion, with most of their revenue coming from licensing RISC-type CPU cores, as well as some neural processing unit (NPU) and graphics processing unit (GPU) IP cores for use in (relatively) low power System-on-Chip (SoC) style silicon chips used in a plethora of electronic devices.
Whilst Arm’s IP is used in SoCs, they are often not the ones doing the actual design of the chips, rather their IP is used as a blueprint to speed up the design time and reduce the engineering cost of the actual chip designers, companies such as Broadcom, Texas Instruments or Mediatek.
For instance, one market where Arm does exceptionally is in smartphone SoCs, where they have a monopolistic grip on the CPU IP used. The Google Tensor G3 used in the Pixel 8 uses Arm CPUs, the HiSilicon Kirin 9010 used in the Huawei Mate XT uses Arm CPUs, even Samsung’s recent Galaxy S24 uses Arm CPUs. The Galaxy S24 uses a Qualcomm Snapdragon 8 Gen 3 chip or a Samsung in-house developed Exynos 2400 chip depending on what region the phone is distributed in, but both versions use licensed ARM CPU IP.
Many automotive chips also tend to use Arm CPUs, for example NXP sell the S32K series of chips to car manufacturers (NXP declared $7,484 million in revenue from the automotive market in 2023). The S32K series all use Arm CPU IP as the core of the chip. Anywhere you might need a low power, efficient but fast processor, you are likely to find Arm IP. This is partially because the CPU IP that Arm provides makes the chip design process much faster and cheaper for design companies by providing works-out-the-box CPU designs, and partially because Arm cores use a RISC based CPUs which tend to be power-efficient.
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What is RISC?
RISC CPUs are often best understood in contrast to their cousins, complex instruction set computer (CISC) CPUs, such as the x86 architecture used by Intel and AMD CPUs. The core idea is that any software that one wants to write to run on any computer needs to be converted into a set of instructions that can be performed by that computer’s CPU. For example, any operating system (like Windows 11 or Android) or software application (like Microsoft Word) or even embedded software (like the software which controls your smart fridge) is normally written in a programming language and then converted (the technical terminology is “compiled”) to a set of instructions which the underlying silicon chip can execute.
The possible set of instructions which the silicon chip can run is called the instruction set architecture (ISA). The ISA is used by chip design engineers to help define how the physical chip itself should be designed, whilst also providing a reference to software engineers used when designing the operating system and software compiler.
The difference in RISC and CISC based designs is that RISC designs use a small number of simple, fixed-length instructions, whereas CISC designs tend to need to support a very large number of complex instructions. The result of this is that RISC chips tend to be very power efficient, which is why they are almost exclusively used in smartphone chips. They are also used in any consumer electronics product where you might want to run software with low power consumption, for example smartwatches, wireless headphones, drones, car infotainment systems etc. However, Arm IP can currently be found in everything from low power microcontroller units to server-grade chips.
What is the threat from RISC-V?
However, the new RISC-V open-source ISA is creating a real threat to Arm’s core business. RISC-V is an open-source architecture, which means anyone can freely use it to develop their own CPU designs which can be fairly easily integrated with existing software (more on this later) without paying any licensing fees whatsoever, and many companies are doing exactly that.
The RISC-V initiative was started in 2010 at the University of California Berkeley, and since then it has received international research funding, including from DARPA and China’s Ministry of Science and Technology. The Chinese government loves RISC-V as an alternative to Arm because it isn’t as directly tied to a western company, and as such has invested hundreds of millions of dollars into promoting and developing it.
In order to understand why RISC-V is a threat to Arm’s business, it is first important to understand the difference between an IP core and an ISA. Arm provides a family of RISC architectures which they update over time (for instance Armv8-A, Armv9-A) – these are just definitions for the instructions that hypothetical CPUs using this architecture would be able to execute. On the other hand, what Arm mostly license to their customers are specific CPU IP cores, sometimes called ‘implementations’ or ‘microarchitectures’, which means they are different types of circuit designs which can run the same ISA.
One CPU implementation might be fast but power-hungry, and another might be slow but more energy efficient, but if they use the same ISA they would be able to run exactly the same compiled set of instructions. Although the CPU design in the Google Pixel 8 and the Galaxy S24 are different designs (or different microarchitectures), because share the same architecture they can both essentially run all of the same software.
Arm provides both licenses for using their CPU cores, as well as licenses to use just their ISA to design your own completely custom CPU (as Apple have done with their M-series Apple silicon chips), but the future profit from both of these streams faces a threat from RISC-V. It is important to note that RISC-V is just an open-source architecture definition, not a specific CPU core in and of itself. However, it has made it possible to make CPU designs, such as the lowRISC Ibex core completely free to download from the internet, because the architecture they are tied to is completely open source.
The threat to Arm Holdings’ processor IP licensing profits
To start with, several companies internationally have started developing RISC-V based CPUs, including IP and physical chips which are competing directly with Arm’s business. For example, the USA based SiFive and Taiwan based Andes Technology Corp both license RISC-V based processor IP that can be used by SoC integrator companies in their chips and can fulfil many of the same functions that Arm’s CPU cores can.
It is likely that more competition in the CPU IP licensing marketing will drive prices, and by extension profits, down. These RISC-V IP cores have already worked their way into commercial products, with SiFive having licensed processor cores to Renesas Electronics and Tenstorrent. Arm’s bigger competitors have also taken note, with Intel reportedly offering to acquire SiFive for $2 billion. This will damage Arm’s future earnings but perhaps isn’t the biggest threat to their bottom line.
The bigger threat to Arm Holdings is…
As we mentioned earlier, Arm’s licenses (Arm is currently radically rethinking how they perform licensing) can be split into processor IP licenses, which let companies directly use Arm’s CPU cores in their chips, and architectural licenses, which let companies use the Arm architecture to custom design their own CPU cores.
Companies benefit from using the architectural license if they have a strong engineering team and want to create a CPU that can integrate well with other in-house custom-designed chip IP (like with the Apple M-series chips which integrate Apple-designed GPUs and other IP blocks allowing them to make a chip which is very tailor-made for Macs), because it means their custom designed chip can still benefit from being compatible with any software designed to be able to run on the Arm ISA.
The irony here is that Arm charges more for architectural licenses than processor licenses. This is where RISC-V will do the most damage to Arm’s bottom line: why would a company need to pay so much for the rights to use Arm’s architecture when they can directly use the ever-more-widely supported RISC-V architecture which also supports customisation? This saves the cost of an expensive license, a team of lawyers to negotiate the licensing contract for several months, the legal risk of breaking the licensing agreement like with the Qualcomm court case (Qualcomm was a previous licensee of the Arm architecture license) and so forth.
It also gives chip designers arguably more design freedom than if they used the Arm architecture since RISC-V allows CPU designers to pick and choose which parts (“extensions”) of the ISA they want to support in their CPU.
The shift towards using more RISC-V cores in SoCs has already begun in the chip design industry. For example, around 2018 Google developed the Titan M smartphone security module for used in their Pixel phones based on an Arm CPU, but their most recent version of this module, the Titan M2, which has been used since the Pixel 6, switched to using a RISC-V based core.
Other companies such as Seagate and Imagination Technologies have reported developing custom RISC-V cores. This is just the beginning – RISC-V has only started appearing in commercial chips in the last few years because it is a new, unfamiliar architecture to many engineering teams. But when engineering teams are making architectural decisions on the next generation of chips, using Arm will begin to seem like a much less appealing choice.
Where has Arm Holdings still got an advantage?
Nonetheless, in the near future Arm still has some advantages. Firstly, because RISC-V is a new architecture, it is not fully integrated with the software languages that many software developers use. When a software engineer wants to compile a piece of code to run on a specific CPU, they use a compiler to convert their code (high-level language) to instructions (machine code) in that specific CPU’s ISA. Each programming language needs a different compiler to be able to convert the high-level format into machine code in an optimised manner.
Because the Arm architecture has been around for a long time, there already exist compilers for all popular programming languages to convert code to the Arm ISA, whereas RISC-V still doesn’t fully support some compilers or cannot provide optimised compilation (can compile code but doesn’t run as fast as possible), which is an issue because it will cause software running on the RISC-V chip to run slower and degrade the end user’s experience.
It also means some operating systems might not be able to run by RISC-V chips until a dedicated engineering effort is made to integrate them with the ISA. This is only a short-term problem; given that RISC-V is an open-source architecture and software developers love open-source, it will only be so long before full support and optimisation get community developed (excluding full support with Windows and iOS/OS X which will require engineering effort from corresponding companies).
The author writes this with complete confidence because some of the most important software in the world is open-source, like Linux, Android, the GNU Compiler and PyTorch. As of 2025, Arm has an advantage that their CPU architecture can be fully integrated in an optimised manner with a plethora of software including operating systems like Windows, OS X and Android.
Arm has another advantage – they offer a relatively complete array of different IP modules including GPUs and NPUs. This means that they can provide out-of-the-box integration for their NPUs and GPUs with their CPUs. The key point is that many SoC designers often aren’t just looking for a CPU, but rather several different types of IP that they will seek to combine into an entire system.
Software must be compiled to run on the CPU, but often designers will seek to use modules like the GPU or NPU to offload instructions which would take a CPU a long time to process.
Here’s an example – if a system architect were seeking to make a SoC which could run software including a neural network application, they might want to integrate a CPU which would run most of the calculations of the software with an NPU which would process the neural network part of the software (because this would be an energy efficient). However, integrating these two IP modules (the CPU and NPU) can be technically challenging, meaning it requires engineers, time and money. Arm can offer CPU and NPU IP which can be very seamlessly integrated with each other, creating a certain amount of vendor lock-in.
Concluding thoughts
RISC-V does not appear as an immediate threat to Arm to non-technical investors, because its adoption rate in commercial chips is still quite low, but by the time this open-source architecture reaches full maturity Arm will start to lose significant revenue to it. They will face competition pressure on the processor IP that they license to their customers, and will very possibly lose architectural license customers who decide to use the free RISC-V architecture to design their custom CPUs.
Considering the amount of Chinese investment into RISC-V, as well as the fact that there is a lot of enthusiasm for RISC-V in the open-source software community, eventual maturity of RISC-V and its complete integration with software languages and operating systems is an inevitability. As such, investors should start calculating what the damage will be now and not after the dust settles.
